The present invention relates to a memory testing device, and more particularly to a semiconductor memory testing device and an associated method which simultaneously enables a plurality of wordlines to be efficiently and rapidly tested.
Generally the production cost for a dynamic random access memory (DRAM) can be broadly divided into fabrication costs and testing cost. Recent trends indicate that the test costs are increasing as compared to the fabrication cost for these highly integrated DRAM devices.
One solution for reducing this testing cost is to employ a multi wordline testing technique. The multi wordline test is designed to detect leak currents due to drops in threshold voltage when a wordline is in active state. The multi wordline testing is usually performed in such a manner that enables a plurality of wordlines at the same time to test.
As depicted in FIG. 1, the semiconductor test device according to a related art includes a test signal decoder 10 and a plurality of bank control units 16.
The test signal decoder 10 includes first and second burn-in test signal generation units 12 and 14.
The first burn-in test signal generation unit 12 generates a first burn-in test signal TAW that is used to enable a given entire main wordline when any one of burn-in test mode signals TM<1:4> is in an enabled state and when a multi wordline test mode signal T14WL is in an enabled state.
The second burn-in test signal generation unit 14 inputs the burn-in test mode signals TM<1:4> and subsequently generates second burn-in test signals TFX<0:3> which are used to subsequently selectively enable sub wordline testing.
The first burn-in test signal TAW and the second burn-in test signals TFX<0:3> are respectively provided to a plurality of bank control units 16.
Herein, the multi wordline test mode signal T14WL is understood to mean a test mode signal applied by a mode register set (not shown) that can be used to enable ¼ of a given wordline.
As depicted in FIG. 2, each bank control unit 16 includes an address latch unit 20, main address predecoders 22, a main wordline driving unit 24, a sub address predecoder 26, sub wordline driving units 28 and a wordline driving unit 29.
The address latch unit 20 latches any one of the inputted address signals A<0:13> in accordance to a bank control signal BCi and then outputs a corresponding given main address signal BXA<a>.
Each main address predecoder 22 inputs and predecodes the given main address signal BXA<a> outputted from the address latch unit 20 and controls the output of the predecoded main address signals LAXa<0:1> in accordance to the first burn-in test signal TAW.
The main wordline driving unit 24 inputs the predecoded main address signals LAXa<0:1> and outputs a main-wordline driving signal MWLa, in accordance to the predecoded main address signals LAXa<0:1>, to a wordline driving unit 29.
The sub address predecoder 26 inputs and predecodes sub-address signals BXA<0:1> outputted from the address latch unit 20 in accordance to the bank control signal BCi. The sub-address predecoder 26 subsequently controls the output of the predecoded sub address signals LAX01<0:3>, in accordance to the second burn-in test signals TFX<0:3>, to corresponding sub-wordline driving units 28. Each sub-wordline driving unit 28 can then output a corresponding sub-wordline driving signal FX<0:3> to the wordline driving unit 29.
The wordline driving unit 29 drives a plurality of wordline signals WL selected in accordance to the inputted main-wordline driving signal MWLa and the inputted sub-wordline driving signal FX<0:3>.
An operation of the multi wordline test will be described with reference to FIGS. 1 and 2.
The multi wordline test operation is performed when the multi wordline test mode signal T14WL is set at an enabled state and the burn-in test mode signals TM<1:4> is set at a disabled state. That is, the first burn-in test signal TAW is set at an enabled state in accordance to when the multi wordline test mode signal T14WL is set at an enabled state and when the second burn-in test signals TFX<0:3> are all set at a disabled state.
Each main address predecoder 22 outputs the output signal LAXa<0:1> in an enabled state when the inputted first burn-in test signal TAW is in an enabled state regardless of the inputted main address signal BXA<a>. Therefore, the main wordline driving unit 24 outputs all of the corresponding main wordline driving signals MWLa in an enabled state.
The sub-address predecoder 26 outputs the output signal LAX01<0:3> in an enabled state in accordance to the inputted sub-address signal BXA<0:1> when the second burn-in test signals TFX<0:3> are all in a disabled state.
Each sub wordline driving unit 28 inputs a corresponding output signal LAX01<0:3> and subsequently outputs a corresponding sub-wordline driving signal FX<0:3> in an enabled state. Therefore, any one of the sub-wordline driving signals FX<0:3> is enabled.
The wordline driving unit 29 inputs any one of the sub-wordline driving signal FX<0:3> outputted from any one of the sub-wordline driving units 28 and also inputs the main wordline driving signal MWLa outputted from the main wordline driving unit 24, so that the wordline driving unit 29 can subsequently output any one corresponding wordline signal WL. Therefore, ¼ of a given wordline of an entire wordline can be tested at the same time when performing the multi word line test when using the related art.
Unfortunately, a number of problems can arise when using the related art to perform multi wordline testing. Since all banks are tested regardless of the state of the bank control signal BCi, then a problem in controlling a voltage drop can adversely affect the accuracy of the testing results of the memory cells. This problem can be further aggravated in the semiconductor test device of the related art when the number of the wordlines which are enabled at the same time is sequentially increased, because the plurality of wordlines driven in previous steps are not precharged when the multi wordline test is continuously performed.
Referring now to FIG. 3, the above noted problem associated with related art semiconductor test devices that are used to continuously perform the multi wordline testing will be further described.
Herein, the bank control signal BCi is provided on a per bank basis, and is in an enabled state corresponding to the active signals ACT1 through ACT4 and is in a disabled state corresponding to the precharge signal PCG1 through PCG4.
When continuously performing the multi wordline test, the first burn-in test signal TAW is maintained in an enabled state as the multi wordline test mode signal T14WL is maintained in an enabled state.
When the active signals ACT1 through ACT4 and the precharge signals PCG1 through PCG4 are sequentially applied, the predecoded address LAX01<0:3> is sequentially changed assuming that the sub address BXA<0:1> is also sequentially changed.
Specifically, the predecoded address LAX01<0> is set to an enabled state as a high level when in synchronization with the active signal ACT1 and the predecoded address LAX01<0> is set to a disabled state as a low level when in synchronization with the precharge signal PCG1. Likewise, the predecoded address signals LAX01<1:3> are set at an enabled state as a high level when in synchronization with their respective active signals ACT2 through ACT4. Likewise, the predecoded address signals LAX01<1:3> are set at a disabled state as a low level when in synchronization with their respective precharge signals PCG2 through PCG4.
In the related art, the sub wordline driving signals FX<0:3> outputted from the respective sub wordline driving units 28 are set in an enabled state when in synchronization with their respective enabled predecoded address signals LAX<0:3>. This operation results in maintaining the previous set states when the first burn-in test signal TAW is maintained in the enabled state set at a high level.
As a consequence, when the number of sub wordlines maintained in an enabled state is increased when performing continuously the multi wordline testing, the number of the wordlines which are set at an enabled state at the same time is sequentially increased, which in turn makes it difficult to continue testing.